1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a memory device structure which minimizes speed delays due to skew between access times of data cells in the operation of a high-speed memory device and which reduces the size of a memory circuit array. The present application is based on Korean Application No. 18291/1995, which is incorporated herein by reference for all purposes.
2. Description of the Related Art
Generally, as capacities of semiconductor memory devices increase, in particular, capacities of dynamic RAM devices, their sizes are accordingly considerably enlarged. Meanwhile, owing to the development of process technology, the width of bus lines in such devices narrows notably, thereby increasing line loading to the memory circuits.
Nevertheless, the need for faster, lower power-consuming and higher bandwidth memory products continues to grow, and will continue to grow for the foreseeable future. To respond to such trends, various memory architectures are under development, along with diverse technologies directed to feature enhancement.
FIG. 1 shows a data path and circuit array layout in a conventional semiconductor memory. In this structure, there are provided memory cell array blocks 100; column decoders 40 disposed between two memory cell array blocks; row decoders 30 arranged toward a chip center portion of each memory cell array block; data input/output buffers 4 disposed to one side of the center of the horizontal direction of one of the memory cell array blocks 100; and data sense amplifiers and data input drivers 2 which connect each of or a plurality of data input/output lines 1 with a switching device 20. Output data lines 3 are wired to the center area of the chip and are connected to respective switching devices 20. Accordingly, data is thereby transferred to data bus 5 which is connected with data input/output buffer 4.
In such a memory structure, when memory cells at both side ends of the memory cell array block 100 are simultaneously accessed, the difference between the speeds at which data is retrieved from both cells increases in accordance with the memory chip capacity. Also, since the data sense amplifiers 2 are arranged to connect to each or a plurality of the data input/output lines 1 in the memory cell array block 100, the memory circuit array area increases considerably. Furthermore, when a large amount of data must be concurrently outputted in the memory cell array to implement high bandwidth, an even larger circuit array area and increased power consumption are required.